The future of computing has arrived, according to China’s Huawei Technologies.
The Shenzhen-based technology giant’s launch this week of the Mate XT 2 smartphone, its first commercial product powered by a processor with a novel architecture, is a public test of the Chinese tech giant’s claim to have invented a new chip design paradigm.
It is also its first step to rewiring artificial intelligence (AI) infrastructure.
The phone’s chip, the Kirin 9050 Pro, is the first designed according to the LogicFolding architecture based on the Tau Scaling Law that Huawei unveiled in May as an alternative to Moore’s Law, which has guided conventional chipmaking for decades. LogicFolding layers integrated circuits on top of one another to boost performance rather than shrink them to fit in a single layer.
Launching the trifold phone at an event in Guangzhou on Monday, Richard Yu Chengdong, chairman of Huawei’s consumer business group, said the 9050 Pro chip improved the phone’s overall performance by 42 per cent compared with Mate XTs released last year. That gives it value for consumers willing to pay 19,999 yuan (US$2,980) to acquire one. The value for Huawei is as a proof of concept for LogicFolding and Tau scaling.
The company’s ambition is to deliver within five years a transistor performance equivalent to that of a 1.4-nanometre process node – seen as the next generation of semiconductors – without relying on improvements in the lithography tools used to etch them.
Chip foundries outside China expect to be producing 1.4nm process node semiconductors within two to three years. However, sanctions imposed by the United States in 2019 banned the sale to Chinese companies of the most advanced extreme ultraviolet (EUV) lithography machines, needed to produce chips with process nodes 3nm and under.
Now Huawei expects to be in a position around 2030 to use LogicFolding for a new generation of its flagship Ascend AI chip, showing China can establish a self-reliant semiconductor ecosystem.
Why Tau Scaling Law instead of Moore’s Law?
Transistors are the tiny electronic switches that control the flow of electricity on chips. For decades, the global semiconductor industry has followed Moore’s Law. Named for Gordon Moore, co-founder of US chipmaker Intel, it was his observation that the number of transistors on a microchip doubles roughly every two years for a near doubling of computing power and speed.
How does it work? Increasing transistor density reduces the distance electricity travels, signals move faster and the chip processes data at higher speeds. Having more transistors allows for more complex circuits that can handle heavier and more complex workloads.
With the US ban on EUV machines hindering Huawei’s further pursuit of Moore’s Law, a new paradigm was needed. It arrived in May. In a research paper presented by Huawei “chip queen” He Tingbo at an international symposium in Shanghai, she described the Tau (Ï„) Scaling Law as a new guide to the “evolution of both semiconductors and electronic systems”.
Instead of being geometric and making performance gains by shrinking transistors, He’s law is temporal and does so by reducing latency – the delay to signals. In other words, He’s dimension focuses on time, while Moore’s focuses on space.
He’s law works by shortening the distance signals travel between neural, graphics and central processing units and digital signal processors through having them move vertically rather than horizontally, thereby reducing the amount of power needed and lowering resistance and capacitance; with less electrical charge to store, transistors and circuits turn on and off more quickly.
According to He, this approach has overcome a bugbear of ever-increasing transistor density: heat. Moore’s Law ran up against the expiry of another law called Dennard scaling. This held that electrical voltage shrank in line with the dimensions of transistors, so that power consumption for a given area of silicon stayed constant.
Dennard scaling broke down around 20 years ago. Since then, as chip sizes stayed roughly the same while transistor counts continued to increase sharply, the amount of power dissipated per square millimetre also rose sharply, concentrating intense heat in a tiny space that was difficult to cool. Too much heat causes transistors to leak energy and degrades performance.
With LogicFolding, crucially, signals travel shorter distances on a chip, requiring less power and generating less heat, as He argued in another research paper published days ahead of the Kirin 9050 Pro’s launch.
Despite heat being “the sharpest concern” for the Tau Scaling Law, the company’s measurements for its new Kirin chip “turned that objection upside down”, He wrote. Her paper said the chip ran cooler than its predecessor while packing 55 per cent more transistors per square millimetre and cutting power use by up to 66 per cent on key tasks.
Analysts at brokerage Kaiyuan Securities noted that, as well as the heat reduction from LogicFolding, the chip design places the most heat-sensitive modules in positions with the clearest heat dissipation paths.
How is Huawei’s use of 3D stacking different?
The functional heart of a microchip is the semiconductor die, a small, flat piece of silicon housing the transistors, resistors and capacitors that perform electronic operations. Chip manufacturers already employ so-called 3D stacking to package dies together in order to increase computing power, but Huawei’s use of 3D stacking is different: it occurs within the die.
Instead of designing each die in two dimensions, then combining them, Huawei treats its multilayer die as a unified three-dimensional design space in which two silicon wafers are stacked face to face and connected using a hybrid bonding technique.
Huawei describes the difference as the gap between two stand-alone buildings linked by a corridor versus its own approach of having a single duplex structure with staircases throughout, according to website ChinaBizInsider.
Other semiconductor design teams, including Intel’s, continue to believe in Moore’s Law, betting that they can keep coming up with ever smaller chips through innovations in transistor design, materials and packaging. In June, IBM unveiled a 0.7nm chip fabrication process that uses 3D vertical stacking. Some companies are doing away with the chip and instead packaging together multiple chiplets, each of which specialises in a single function.
For those who believe Moore’s Law no longer applies, emerging technologies such as quantum processors (see China Future Tech briefing) and photonic chips (see China Future Tech briefing) hold appeal, although sceptics question whether they can fully replace classical processors.
As an emerging technology, He’s Tau scaling and LogicFolding approach faces much scrutiny. Independent benchmarking of the Kirin 9050 Pro chip will be performed to validate the company’s claims, and He’s claims about its superior heat management will be put to the test.
There also will be questions about packaging capacity where integrating multiple chips is involved, and the degree of design complexity LogicFolding allows. Chip-to-chip connectivity will be vital, said Ethan Qi, associate director of the Greater China team at Counterpoint Research.
“In the age of AI, whoever masters the die-to-die protocols will be able to secure market dominance like Nvidia,” he added, referring to the US tech giant that dominates the market for GPUs and AI hardware.
A key question is how big a yield will be achieved in volume production of the new flagship chip, which will probably involve China’s largest chip foundry, Shanghai-based Semiconductor Manufacturing International Corp (SMIC). Yield is the percentage of usable dies produced from a silicon wafer compared to the total number of potential dies it could produce. If producing LogicFolding chips is difficult to master and high error rates depress yield, production costs will rise.
Chinese computing industry partners will also have to embrace Tau scaling for it to serve as the basis for a broader, self-reliant ecosystem. On that front, early signs have been positive.
In June, Beijing-based Empyrean Technology, a major provider of electronic design automation (EDA) software, unveiled a physical verification platform for three-dimensional integrated circuit design. Earlier, researchers at Peking University unveiled a prototype EDA tool tailored to Huawei’s LogicFolding architecture.
Still, it could take four to five years for the domestic chip supply chain to develop the necessary tools, including EDA, to fully support Huawei’s new chip architecture, Chinese semiconductor research firm ICWise said in a research note in late May.
Additional reporting by Coco Feng and Howard Liu
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This article originally appeared on the South China Morning Post (www.scmp.com), the leading news media reporting on China and Asia.
